The present invention relates to semiconductor devices, and more particularly to a method and system for tailoring core and periphery cells in a nonvolatile memory.
Conventional semiconductor devices, such as conventional nonvolatile memory devices, typically include a core region and a periphery region. The core typically includes cells of one type, such as nonvolatile memory cells. The periphery typically includes logic devices such as transistors. The cells in the core typically include a plurality of gate stacks. A source is positioned at one edge of each gate stack, while the drain is at the opposing edge of the gate stack. Each gate stack typically includes several gates, such as a floating gate and a control gate separated from the floating gate by an insulating layer such as oxynitride oxide (ONO). Other layers such as a Wsi, and polysilicon and SiN capping layers may also be provided. The floating and control gates are typically made of polysilicon. The gate stacks at the periphery typically include a single polysilicon gate. Periphery sources and drains are generally located at opposing edges of the periphery gate stacks. Spacers are also located at the edges of the core and periphery gate stacks.
In order to fabricate the conventional semiconductor device, the gate stacks at the core and periphery are generally formed first. A nitride layer is deposited over the core and the periphery. The spacers formed are composed of the nitride layer. A mask which exposes only the source and drain regions of the core is provided. The source and drain for the core are then implanted. In addition, an LDD mask and implant are provided for the periphery. The nitride layer is then etched at the core and the periphery, using a mask which exposed the source and drain regions at the core and the periphery. The spacers at the core and the periphery are, therefore, formed concurrently. The periphery sources and drain implant is then provided. Processing of the semiconductor device can then be completed.
Although the conventional method for forming the cells in a semiconductor device functions, one of ordinary skill in the art will readily recognize that the conventional method results in spacers which are the same at the core and the periphery. Thus, the spacers at the core have the same thickness as the spacers at the periphery. The spacers at the periphery are desired to be thick to separate the source and drain implant from the gate stacks in the periphery, thereby avoiding the hot carrier effect. However, the spacers at the core need not be as thick as the spacers at the periphery. Consequently, the spacers at the core may be thicker than desired. As a result, cells in the core may be larger than desired. Furthermore, is the spacers may fill the region above the sources in the core making it difficult to form silicided source lines.
Accordingly, what is needed is a system and method for providing a semiconductor device having spacers tailored to their function. The present invention addresses such a need.
The present invention provides a method and system for providing a semiconductor device. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system comprise providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The plurality of core spacers resides at the first plurality of edges and has a thickness. The plurality of periphery spacers resides at the second plurality of edges and has a second thickness greater than the first thickness. The plurality of core sources resides between the plurality of core gate stacks. The plurality of conductive regions is on the plurality of core sources.
According to the system and method disclosed herein, the present invention allows the spacers for the core and the periphery to be individually tailored. Thus, for example, the core sources can be exposed for a CoSi layer, which reduces the resistance of the core source lines.